AI Great Powers Part 8: The Memory Clock and the Taiwan Window
China's logic ramp took nine years from decision to volume; run the same clock on memory and self-sufficiency lands ~2033, a date with uncomfortable strategic geometry on both sides.
China has run exactly one sanctioned-chip-capability ramp before, start to finish, on the public record. It took nine years from the decision to the volume. It is now running a second one, on memory for AI accelerators, and we know when the decision was made. This post runs the clock, and then sits, carefully, with what the date means for potential conflict with Taiwan.
Two clocks. China’s logic ramp ran nine years, decision (2014, Big Fund I) to 7nm volume (2023, Kirin 9000S); the memory clock (committed ~2022, funded 2024) is the same curve offset onto the 2024 decision, due ~2033, with the 2031–2038 arrival band drawn as the fade it is.
Results up front
This is the most leadership-facing post in the series, so the bottom line goes first. If we assume AI Accelerators stay a strategic asset, then export controls stop being a geopolitical lever around 2033.
China reaches “enough” domestic AI memory (the point where high-bandwidth memory stops capping its AI-hardware output) around 2033, with an honest band of 2031 to 2038. Two routes land on that date: a supply-curve projection of when the memory-fed ceiling rises to meet what China’s chip plants could otherwise feed, and a historical analog. China’s last sanctioned-capability ramp, in logic chips, took about nine years from funded decision to meaningful volume, and the memory decision was funded in 2024. Until then, every year is a year of dependency: China’s deployed AI fleet runs partly on imported and stockpiled foreign parts it cannot replace at tempo.
That is the memory clock. The uncomfortable part is what it does to the Taiwan window, and it cuts both ways. Read one way, the clock counsels Beijing to wait: a war now severs the very inflows the AI buildout runs on. Read the other way, it says the leverage decays: every year of ramp shrinks what export controls and exposure can hold at risk. I am not going to pretend those two readings resolve. They don’t. This post sharpens both blades, then says plainly that a capability clock is one input to a war decision, not a forecast of one.
A scoping note: every claim here is time-boxed (imagery to collection date, documents to filing date, “as of June 2026” the series freshness stamp); a built shell is not an operating fab, and where I project, I label the projection and its confidence. The ~2033 date is exactly that: a reasoned analog projection with a band, not a certainty forecast. The method is the argument, so the method comes next.
The clock China already ran
You cannot ask a filing about 2033. Filings run out around 2028. That is where the construction permits, tool orders, and prospectus capacity tables in Part 6 stop. Past that horizon you can refuse to estimate, extrapolate a trend line, or find an analog: a comparable process the same actor has already run end-to-end, and reason from its shape. Analogs are the weakest form of evidence in this series and the only honest tool for this question, which is why this post spends as much time on what would break the analog as on the date it produces.
The analog here is unusually clean, because China has run this exact play before, once, in public.
In 2014, Beijing converted aspiration into a funded, top-level commitment to indigenous logic chips: the June 2014 National IC Development Guidelines and the September 2014 “Big Fund I”, ¥138.7 billion (the fund’s full raised size, distinct from the ¥132.1bn that Part 5 traces from ALL national funds into the fab atlas), about US$22 billion at the time. Nine years later, in 2023, SMIC shipped 7nm-class logic at meaningful volume: the N+2 process inside the Kirin 9000S that surfaced in Huawei’s Mate 60. The capacity curve since: roughly 20k wafers per month of ≤7nm in 2023, 45k in 2025, 60k in 2026, on a path to ~80k in 2027.
Decision to volume: about nine years. And that nine years was not idleness. It is what a from-scratch, sanctioned semiconductor capability physically takes:
The tool chain has to be rebuilt link by link. A chip process is hundreds of steps, each needing a qualified tool; when the critical tools are export-controlled, each must be domestically developed, qualified on a production line, and integrated, largely serially, because each tool’s qualification depends on the steps around it behaving.
Yield is learned, not bought. Yield curves bend with accumulated volume: you find defects by running wafers, fix them, run more. But customers only take volume when yield is tolerable: a loop that turns years of capital into years of calendar. Money compresses this less than people assume; SMIC’s 7nm took nine years with deep, patient state backing.
How to read it: the timeline runs left to right from the 2014 decision point; the labeled boxes are dated public milestones; the red curve (right axis) is ≤7nm capacity in thousands of wafers per month; the blue curve (left axis) is aggregate all-node capacity in millions of wafers per month, for scale. What to see: nine years of near-zero on the red curve before it lifts. The ramp’s shape, not its endpoint, is what we borrow. (Chart: HuaweiFabHunt Stage 54, June 2026)
Running the same clock on memory
Now the second clock. HBM (high-bandwidth memory, the specialized stacked memory every serious AI chip must be packaged with) is China’s single binding shortage; Part 6 established that and stops its story at 2028. This post owns what happens after, and for that we need HBM’s decision point.
It is datable. HBM was not in the 2014 framing at all. It became existential only when advanced AI accelerators did. The October 2022 US export controls made HBM-fed indigenous AI silicon the chokepoint: committed. Then 2024 made it funded and explicit: Big Fund III (¥344 billion, about US$48 billion, May 2024) weighted toward equipment and memory; the December 2024 US controls naming HBM itself; and the Huawei–CXMT consortium forming around the domestic ramp. Committed about 2022, funded 2024. HBM in 2024–2026 sits roughly where logic sat in 2014–2016: just entering its funded ramp.
Slide the logic ramp’s shape onto that decision point and you get the projection, run as two scenarios because HBM has a fast half and a slow half. The fast half is the memory die itself: CXMT was already a DRAM maker, so HBM-grade DRAM extends an existing base: first HBM samples arrived about two years after the 2022 commitment, essentially as the 2024 funding landed (HBM3 samples to Huawei followed, reported April–May 2026, still tentatively sourced). The slow half is the back-end: drilling thousands of microscopic vertical interconnects through each die (TSV, through-silicon vias), welding the dies into towers under heat and pressure (TCB, thermo-compression bonding, the precision tool China can no longer buy), and getting whole stacks to test healthy (KGSD, known-good stacked die, the yield number that actually matters). That back-end is genuinely from-scratch and genuinely sanctioned (the same situation as SMIC’s 7nm in 2014), so the nine-year clock is applied to the back-end, the binding term. The optimistic scenario lets the front-end advantage pull the curve up; the conservative scenario holds the analog strictly.
How to read it: the red curve is the optimistic HBM-fed output scenario, the orange curve the conservative one; the light-blue band at top is what China’s logic capacity could otherwise feed (the 24–60× headroom); the grey band hugging the HBM curves is the comparable packaging constraint, co-binding with memory; the marked crossings are where memory stops capping the realistic build ambition. What to see: the optimistic crossing lands ~2033; the conservative curve crosses at ~2038, at the chart’s right edge (the memo carries that branch as ~2036–2038), and neither HBM curve reaches the logic band’s headroom this side of the late 2030s. (Chart: HuaweiFabHunt Stage 54, June 2026)
Three results, in descending order of confidence:
HBM stays the binding constraint through at least ~2028. This end is anchored to filings and the Part-6 model, not the analog. High confidence.
“Enough HBM” to populate a realistic national build of a few million accelerators a year arrives ~2033, band 2031–2038. The supply-curve crossover and the decision-lag analog (funded 2024 + ~9 years ≈ 2033) converge. But convergence of two methods that share an author is comfort, not proof. Estimate-grade; the band is the right way to read it.
HBM never saturates logic’s full headroom before the late 2030s. China’s logic plants can feed 24–60× more accelerators than its memory can populate; memory, not logic, not lithography, sets China’s AI-accelerator clock for roughly a decade.
What would make the analog wrong? Be specific, because this is where the argument lives or dies. The analog assumes HBM’s binding step behaves like a from-scratch sanctioned capability, as 7nm did. It breaks fast if domestic bonders qualify at volume yield years early, or if policy reopens foreign HBM supply. Either pulls the date toward 2031 or makes it moot. It breaks slow if the back-end yield curve stalls the way CXMT’s 2026 program already has (direct evidence for the conservative branch, and why the band’s right edge sits at 2038). One structural disanalogy cuts against the optimists: logic ramped partly on a stockpile of foreign lithography tools bought before the bans; nothing in the tool-vendor record suggests an equivalent pre-ban depth of HBM-grade bonders. The analog is not a law of physics. It is the best-calibrated ruler available, laid against the only comparable ramp on record.
The meter while we wait: dependency, measured
Between now and that crossover, the dependency has units. The domestic ceiling is ~225k 910C-equivalent accelerators in 2026 (P10–P90: 192–270k), rising to ~1.0M in 2028 (821k–1,229k); Part 6 derives those numbers and shows why Huawei’s reported ~600k target for 2026 (roughly twice the ceiling) is unreachable from domestic supply. At the data-center layer, that same ceiling re-expresses as a repeatable domestic flow of about 200–310 EFLOPS-FP16 per year (an EFLOPS-FP16 being a billion-billion AI calculations per second in the half-precision arithmetic AI training uses, the unit China’s official compute statistics quote). The flow figure is the fab ceiling translated, not an independent estimate; Part 7 owns the derivation.
Hold the flow against the ambition. National compute targets imply growth of roughly 400+ EFLOPS-FP16 a year. A single facility (Zhongwei, in Ningxia) is a 2.77 GW campus targeting 800 EFLOPS by 2027: several years of the entire national chip flow, alone. By 2028, on Part 7’s projection, sustainable chip supply covers about 47% of the AI-compute ambition in the low case, 69% in the base case, and 102% only in the high case. And the high case requires both CXMT’s HBM reaching mass production and renewed NVIDIA access, which Beijing has so far blocked on its own account.
That is what “every year is a year of dependency” means in numbers. The halls exist. The ambition is funded. The chips are the missing term, until the memory clock runs out.
The window, honestly
Now the part that earns the title, and the part I will not pretend to resolve.
The strategic discourse already has a date in it: 2027, the “Davidson window,” after the admiral who told Congress in 2021 the Taiwan threat could manifest within six years, since reinforced by then-CIA Director William Burns, who said publicly in 2023 that US intelligence indicated Xi had instructed the PLA to be ready by 2027. I am not going to adjudicate that debate; readiness instructions are not decisions to act, and the people who own that question work from evidence I do not have. What I can do is put my clock next to theirs and note that they measure different things. If both dates are roughly right, there is a gap (2027 to ~2033) in which the PLA may be ready but the hardware base underneath China’s AI ambitions is not yet self-sufficient. What does that gap do to incentives? Two readings, pointing in opposite directions.
The case the clock makes for delay. China’s AI buildout currently runs on inflows a war would sever on day one: the decaying overhang of pre-ban foreign silicon and memory that fed 2025’s deployments (Part 6 does that arithmetic), gray-market accelerators, and foreign tool service and spares at the plants still allowed to buy them. A war in the gap (or even a blockade-and-sanctions spiral short of one) does not pause the date; it pushes it years past 2033, plausibly indefinitely, because the ramp itself is partly import-fed. On this reading, the dates speak for themselves: a war in 2027 would be fought with that dependency intact; a war in the mid-2030s would not. And the pattern Beijing has already run once in chips, endure then indigenize, suggests it knows the difference.
The case the clock makes for urgency. Now read it from the other side of the strait, and of the Pacific. The chokepoint’s coercive value is a depreciating asset on exactly this schedule. Every year of ramp means more domestic stacks, more qualified domestic tools, more facilities, and so less that export controls can deny and less that exposure can hold at risk. The leverage Washington spent five years building (Part 10 scores it) is strongest today and weaker every year; so is the deterrent value of China’s hardware vulnerability itself, much of which sits within easy reach of Taiwan: 13 of China’s 14 critical AI-hardware facilities lie within 900 km of the island, geometry Part 9 maps in full. On this reading, those counting on China’s dependency to restrain it should note the restraint’s expiry date.
And the honest third reading. Both arguments treat a capability curve as if it were a war decision. It is not. Wars start, and fail to start, for reasons this analysis does not touch: political imperatives, leadership perception, military readiness in domains far from semiconductors, alliance cohesion, accident. Analysts who predict wars from capability windows have a poor record; the windows that mattered are mostly visible only in hindsight. What this post establishes is narrower and, I think, more durable: it bounds one variable. It tells you when one specific argument (”Beijing’s AI-hardware base cannot yet stand alone”) stops being true, with a band and named triggers. A planner should treat ~2033 as a monitored variable, not a prophecy: one input to net assessment, sitting alongside a dozen variables this series cannot see.
I take both blades seriously. I decline to pick one.
What moves the clock
Because the date is a projection, the responsible product is not the number. It is the watch list that tells you when the number is stale. Three movers dominate; Part 10 carries the full indicator set:
Domestic HBM-grade bonders. The single highest-leverage lever. As of June 2026 the gating tools remain foreign and embargoed; domestic candidates are at validation stage, not volume. A domestic bonder qualifying at volume with acceptable stack yield pulls the clock toward 2031.
CXMT’s HBM3 ramp. The binding facility’s mass-production timeline has already slipped toward late-2026/2027: the strongest current evidence for the conservative branch. Continued slip pushes the clock toward 2036–2038; a clean volume ramp at healthy yield pulls it back.
Huawei’s 950 series and in-house HBM. Huawei’s next accelerators pair a monolithic die with its own proprietary memory stacks. Reported order books are demand-side noise; the supply-side tell is confirmed shipments at scale on in-house memory. If that arrives early, the analog’s offset needs re-examination, in China’s favor.
None of the three had fired as of June 2026. The clock, for now, reads ~2033.
The two clocks, carried forward
Part 9 takes the window’s other coordinate, not when, but where: the physical geometry of what China’s AI buildout exposes. Part 10 closes the series with the scorecard and the standing watch.
The compressed mental model: China’s path to AI-hardware self-sufficiency is not a wall and not a sprint. It is a clock: wound in 2022, funded in 2024, running at the measured pace of the only comparable ramp on record, due around 2033. The window question is not whether the clock is running. Everyone in the room can count. The question each capital must answer for itself is what to do with the window that is closing: the window of China’s hardware dependency, and of the leverage that dependency confers.
This analysis bounds the variable. It does not pick the war. Neither should the clock.
Receipts
Full ledger on my substack
Load-bearing claims in this piece:
Logic ramp analog: decision 2014 (Big Fund I) → 7nm volume 2023 (SMIC N+2, Kirin 9000S) ≈ 9 years; ≤7nm capacity 20k (2023) → 45k (2025) → 60k (2026) → 80k wpm (2027)
HBM decision point: committed ~2022 (Oct-2022 controls), funded 2024 (Big Fund III + Dec-2024 HBM controls + Huawei–CXMT consortium): public-sourced dates; high confidence on the dates, the “decision-point” framing is interpretive.
“Enough HBM” ≈ 2033 (band 2031–2038); two routes converge; HBM never saturates the 24–60× logic headroom before the late 2030s: ; estimate-grade analog projection, not a forecast of certainty; the two converging routes share inputs and an author.
Ceiling endpoints: ~225k 910C-eq 2026 (P50; P10–P90 192–270k) → ~1.0M 2028 (821k–1,229k); Huawei’s ~600k 2026 target ≈ 2× the ceiling: AC-01/AC-15/AC-06; derived in Part 6.
Flow framing: ~200–310 EFLOPS-FP16/yr repeatable domestic flow (the fab ceiling re-expressed, not an independent estimate); 2028 chip-backed share 47/69/102% low/base/high; Zhongwei 2.77 GW targeting 800 EFLOPS by 2027: derived in Part 7.
13 of 14 critical facilities within 900 km of Taiwan: stage-55 strike geometry; mapped in Part 9.
Watch states as of June 2026: domestic bonders validation-stage; CXMT HBM3 slipped to 2H-2026/2027; 950-series in-house-HBM volume unverified: forward-indicator tracker W1/W5/W4; detailed in Parts 6 and 10.
What would change my mind (as of June 2026, none has fired): (1) a domestic HBM-grade bonder qualifying at volume yield (pulls the clock toward 2031); (2) CXMT HBM3 reaching genuine 2026 mass production at healthy yield (selects the optimistic branch); (3) a further CXMT slip or a stalled back-end yield curve through 2027 (selects the conservative branch, ~2036–2038); (4) confirmed several-hundred-thousand-unit 950-series shipments on in-house HBM at volume (re-examine the analog’s offset); (5) a policy change reopening foreign HBM supply to China (retires the clock by changing the question). The 2027-window discourse is engaged here as context only; this post adjudicates nothing about intent.
Every imagery claim in this series is stamped to its collection date; document claims to filing dates; “as of June 2026” is the series freshness stamp. The ~2033 crossover is a labeled projection with a band, time-boxed to today’s known fabs and the public decision record. Charts: HuaweiFabHunt Stage 54, June 2026.